Analog Out, progress and FPGA utilization (Patreon)

Hi everyone,

last post is 12 days ago and I feel it's time to report about the changes.

I didn't had that much time, as we were on holiday with the family for 6 of those 12 days, but 2 changes I could still fit into the time.

The first change is the VRAM readback mode. Until some days ago the PSX core could only display data directly through the scaler reading the VRAM area in DDR3 with direct framebuffer mode. 

While this mode is technically still the best way, as pixels are only written and read once from the memory, it has some downsides.

So I decided to implement a readback of the image to be displayed in the core itself, to give it out in the traditional way: the core should now behave like any core with HDMI, Analog out, Filters, etc.

Analog out sync timing is still wrong and must be adjusted. I will probably get a device that can display 240p signals, so I can finetune this myself.

The second change is the CPU register file. 

After a comment in one of my last posts, if I could show the FPGAs ulitilization(how much of the FPGA is used by the core), I made an overview and well, the FPGA is already well filled, nearly 60%.

So after a discussion with a discord member, I decided to cut it down a bit. The result being the CPUs logic size now reduced by more than 25%. This is done with a special type of memory the Cyclone 5 FPGA has, called MLAB, which uses the Lookup tables, normally used for logic functions, as memory.

I will do a seperate post about the single components of the core, their sizes and other details in a few days.

Next task for the core is the MDEC, the video decoder of the PlayStation and the last missing component before work on the CD module will start. You will hopefully see some commits into the github for the MDEC in the next 2 weeks.

Have fun!