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Last Minute Telegrams: Hardware Numb3rs (Patreon)

Published:
2020-06-02 00:41:48
Imported:

Content

Tomorrow I will have Hardware Numb3rs on as my guest for this week's Broken Silicon!  Here is an example video from him:

https://youtu.be/X6RSEU1d-g8

We will be discussing architectural strengths and weakness of Intel Skylake architectures Vs AMD Zen architectures, and also our expectations for Matisse 2 & Zen 3. 


Please put your reader mail below, and remember to be thoughtful, concise, and use good grammar.  We may read your questions on air!

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Comments

qhfreddy

Aside from the usual "how did you get into competitive OCing, what hardware did you like most, etc" I'd like to know what you'd say for anyone who is new to overclocking for a daily system and for people interested in joining fun/competitive overclocking on HWbot.

Anonymous

With the unification of CCXs on Zen 3, will RAM speed be less important? In other words, do you think Zen 3 will be less sensitive to high clock/low latency RAM?

ishould

Something he may know, how much does IPC correlate with frequency? From 3Ghz to 5Ghz, does IPC increase, and if so why?

Anonymous

Thoughts on Intel mesh vs ring bus vs Zen Infinity Fabric in OC/stock scenarios? What's your experience with mesh been like?

Anonymous
>>37940963

IPC is instructions per clock cycle. IPC doesn't increase with frequency, it's a set number. However, you can do more work with more cycles so you'll see higher ST perf with higher freq.

ishould
>>37940963

That's what I thought, but when I commented earlier it was refuted: "No, IPC does change with clockspeed, as latency, bandwidth and various other “uncore” parts influences IPC." - TSPCFS. Just curious if it actually did or not

Matt Hartley

Is the difference between zen3 and zen2 expected to be similar to that of the 3100 and 3300 in gaming due to the ccx redesign?

Durmij

Has he done any testing with lower fclk to try and figure out a ratio between flck increase and usable core frequency? Could give us some insight on where fclk needs to go before we can utilize 5ghz zen cores

Nils

Do you think that any multi-chip CPU design will reasonably negate the latency issues inherent to splitting up cores from eachother or from their memory controller before we see CPUs change over to 3D/2.5D stacking methods? If so how would they go about this and what concessions might have to be made on the software side to achieve this better performance? (say 2 core dies with dedicated memory controllers with each one having its own channel and suffering the interdie latency only for the other half of the system memory)

Janan Clowes

What is it specifically that gives the Skylake based architectures an advantage over Zen in gaming? Is it optimizations done by developers? Is it reduced latency? If it is latency, how does Intel maintain this advantage, and why haven't AMD been able to catch up?

Matt Hartley

Does intel or amd have better branch prediction? A lot of focus is placed on avx instructions, where intel is ahead by a factor of two at the highest end, but what about pure integer arithmetic or bitwise arithmetic? Are these so easy that neither company really has an edge?

Andrew Martin

Three questions: 1. How did AMD increase the IPC from Zen to Zen 2? Was it a combination of the extra L3 cache and the TAGE branch predictor, or were there more changes under the hood? 2. How is IPC improved typically? 3. What do you think Intel's doing differently with IPC starting with Sunny Cove? After Sandy bridge, IPC improvements were pretty poor, but now all the "Cove" generations have a pretty hefty (~20% ) IPC improvement per generation.