FPGA FPU work started (Patreon)

Hi everyone,

there has been good progress in the last week, much more than I thought I could reach. Let's recap the last post:

My soft floating point implementation for the emulator was still missing plenty of instructions. It turned out that the more you learn about it, the faster you get. So in the end I spend less time for all the missing instructions than I have spend for the ADD instruction I began with.

This means, that my emulator now has a low level integer only implementation of the FPU that passes the whole FPU part of the n64 systemtest and also can run games.

With that knowledge I'm now able to start working on the FPGA part.

This time I did it the other way around: after learning that ADD is one of the more difficult instructions, I started with the easier ones and build up the whole FPU infrastructure first:

- exchanging FPU registers with the CPU and Memory

- exception handling

- writing and reading of FPU flags

- executing instructions and store results

And...what can I say...all these things already work!

Today, the core is already able to run the first few subtests from the systemtest that cover these parts, e.g. the subtests for Single/Double ABS

Of course, only very simple instructions(ABS, NEG, MOVE) are implemented yet, but having that stable is a good step, as I can now fully concentrate on the more complicated FPU instructions without worrying about the CPU-FPU interconnect anymore.

Furthermore, this has another great advantage. 2 posts ago I told you that I want to validate the CPU with the systemtest and had to come back last time that it's not possible due to the FPU missing.

Well, the current state of the FPU is already got enough for these tests, as they have only been saving the FPU state using the transfer commands, which already work.

Thanks to that I can also tell you today that most of the CPU tests I mentioned last time work now. Only the "Traps" subtests are not working yet, which is no surprise, as the instructions checked within this subtest are not fully implemented yet.

Overall I'm very happy with the progress. The project is much further than I could have imagined 1 week ago when I wrote "I will be busy for some weeks...before I can start working on the FPGA part"

The FPGA part however will not be done that fast, as I have to care for resource usage and clock speed/timing and cannot just write down the logic, but overall I'm much more optimistic than I was some weeks ago about this whole FPU topic :)

Have fun!