Release 2022 09 25 for PSX core (Patreon)
Content
Hi everyone,
the accuracy research and fixes are about halfway through now and everything seems stable so far, so it's a good time for a release.
The last two days I could also fix some long outstanding bugs that triggered randomly:
- a bug with the memcard, where the game would not see the content of the memcard until you select it again in OSD
- a bug with loading a savestate, that lead to the core hanging until you reset in OSD or load the state again
Due to that, I couldn't make it with the promissed article this weekend, but I will try to get it done until next weekend.
In the next weeks I will continue with writing tests and implementing the findings. On the list to test/validate/improve in october are:
- CPU instruction fetch from uncached memory and BIOS
- DMA transfer speeds
- MDEC decompression timing
- Gamepad and Memory card access timing
That's it for today. The whole changelog for the release follows below.
Thanks for your support and have fun!
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features:
- implement 3 different turbo speeds
- Move datacache into CPU -> speedup when using turbo setting "high"
fixes/changes:
- fixed memory card loading edge case leading to memory card data not being available
- fixed wrong savestate slot index when loading core
- fixed edge case where loading a savestate would hang up the core until reset is triggered
- fixed CPU blockLoadforward edge case (CPU test from pcsx-redux is now pass)
- many cleanups and resource reductions, FPGA logic went from 97% to 93%
accuracy improvements:
- Memory: CD register bus is now using extbus logic
- Memory: extbus timing modified when using PStrobe together with RecP(CD timings)
- Memory: adjust timings for BIOS reads
- Memory: rework sdram -> instruction cache interface, reducing cache fetch time by 1 cycle, fulfilling test against hardware
- CPU: implement out-of-order load pipelining
- CPU: implement readback of CACHECONTROL register
- CPU: make instruction fetch stage fully independent of data fetch stage
- DMA: add timing cost for ram page switch and refresh
- DMA: reduce initial overhead by 2 cycles
- Timer: implement non-retrigger mode by using Mode bit 6