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Hi everyone,

with first games running in my emulator, I finally feel confident enough to make it public: I'm working on a Playstation core for MiSTer FPGA.

After two not so well known systems, I wanted to do something more mainstream again. Also, unlike many other, I really like those early 3D titles.

As always, I'm doing an emulator in C++ before writing the FPGA core in VHDL. This is very important this time to understand the system as it's really huge. None of my cores until now had so many components working hand in hand together.


It took me 8 weeks now for this stage of understanding and implementing:

- CPU fulfills all instruction tests

- GTE fulfills all opcode tests

- GPU should be ok, some edge cases are left

- DMAs are all implemented, no testrom available unfortunatly

- MDEC is implemented and working so far.

- CDROM is halfway implemented, only data, no audio tracks playback yet

- Gamepad is digital only without Memory card

- Sound only has register and DMA interface, no internal processing yet


The emulator itself is calculating at a cycle level for every component, e.g. the CPU pipeline with all 5 stages, so it behaves very much like the FPGA will later on.

I have the luxury that noone will ever play with this emulator, so I don't need to optimize for speed. It only runs at 30-40% of the original speed on my fast PC and that will likely only drop lower.

Still, this is way faster than VHDL simulation and helps me a lot to really test and debug into the games and understand how everything works, so I can do a clean implementation in VHDL from the very start.


Will it work on the MiSTer? This is still not 100% sure. 

The VRAM in the playstation differs very much from the DDR3 on the DE10-Nano but must be fit into it as good as possible.

Also the Sound RAM is 512Kbyte big, so it must be placed either in SDRam or DDR3.  As I haven't researched how much bandwidth it really needs, I cannot say for sure if it will work. It may require a second SDRam for sound, but I want to avoid.

For the schedule of this project:

As I want to have more games running in the emulator first and also need to do some cleanup, I assume it will be another 4 weeks of emulator work before I can start with the FPGA implementation.

With that in mind, my personal goal is to have 1 game playable on MiSTer by end of this year, no matter which it is. This might be too ambitious, but I need to set myself any goal.


Now let's talk about the big elephant in the room: 

Isn't there a PSX core in development already?

Yes, there is and even with the development stalled or slowed down, they have done great work over the last months and years.

So I was asked by some of you if I would continue the core and I fear that I will not, but I want to tell you why, as I know many of you supported the project and might be sad now.

For me, writing a core myself is all about knowledge and not about existing code.

I worked in the past on systems I don't know well, like the AO486 and NES and even without modifying these much,  mainly adding something new, it was very hard for me to find my way through.

For PSX this would be way worse. To find bugs deep inside later on, in such a complex system, without having it written in the first place, sounds unbearable for me.

I need to know every little detail myself to feel confident enough to tackle such a huge task.

The process to learn all these things is...writing code myself. So if I need to write it anyway to understand it, I can just use that.

It also solves the problem of the language barrier(Verilog vs VHDL) and allows me to implement savestates for all modules from the very start.

Anyway, I really hope Laxer will continue his work. Having two adjacent projects running can help each other.


That's it for now. 

I know that it's gotten silent here, but that's the nature of doing something new that takes a lot of time.

As soon as the FPGA development starts, there will be more frequent updates for sure.

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Comments

birdybro

http://www.citylan.it/wiki/images/5/5a/Mb814260.pdf - Datasheet for the DRAM used in the SPU, Sony used MB814260-70. I think laxer3a was planning for the SPU to SDRAM primarily because of latency concerns.

David Filskov

Impressive!! - way to go :) - thanks a lot! - Hey, isn't / wasn't there someone else working on a PSX core too?